A gate stack integration according to a current RMG process is illustrated in FIGS. 1A through 1D. FIG. 1A illustrates the formation of an interface layer (IL) and a high-K (HK) dielectric layer in both N-FET and P-FET gate trenches 101 and 103, respectively, on a substrate 100. Adverting to FIG. 1B, a p-type work function (pWF) metal layer 105 (e.g., titanium nitride (TiN)) is deposited. Next, as illustrated in FIG. 1C, the pWF metal layer 105 is selectively removed from the N-FET devices by a patterning and etch process. Adverting to FIG. 1D, an n-type work function (nWF) metal layer 107 is deposited on both N-FET and P-FET device gate trenches and a gate metal 109 (e.g., aluminum (Al)) is deposited.
For 20 nm and beyond technology nodes, the threshold voltage (Vth) is adjusted by Al diffusion to the gate stack from the gate metal (e.g., titanium aluminide (TiAl) or Al). However, Al diffusion may also cause high leakage currents to the gate stack resulting in time dependent dielectric breakdown (TDDB). Such leakage currents especially affect N-FET devices. Thus, the utilization of nWF metals to adjust Vth has been very selective depending on the subsequent metal layers (e.g., TiN, tantalum nitride (TaN)) in the RMG process and their thickness. Further, RMG processes are made more complicated by the additional metal layers.
A need therefore exists for a methodology enabling reliable threshold voltage adjustment with a simplified post gate (PG) patterning, and the resulting device.